Telecom Hardware Solutions Conference & Exhibition

Co-Sponsored by:
International Microelectronics And Packaging Society (IMAPS)
&
Surface Mount Technology Association (SMTA)

Advance Program

Doubletree Hotel
7120 Dallas Parkway
Plano, Texas 75024
Get Directions
P: 972-473-6444; F: 972-473-4225
May 15-16, 2002

General Chair:
Walt Marcinkiewicz, Sony Ericsson Mobile Communications
walt.marcinkiewicz@sonyericsson.com  

Technical Program Co-Chairs:
Martin Goetz, Alpine Microsystems
mgoetz@alpinemicro.com 

Viswam Puligandla, Nokia Mobile Phones
viswam.puligandla@nokia.com 

IMAPS President:
Charles Bauer, TechLead Corporation
Chuck.Bauer@TechLeadCorp.com 

SMTA President:
Rod Howell, Libra Industries
rhowell@libraind.com 

Professional Development Courses:
Wednesday, May 15
9 am - Noon

Exhibition Hours:
Wednesday, May 15
10 am - 7:30 pm
Exhibit Hall Reception
6 pm - 7:30 pm

Thursday, May 16
10 am - 4 pm
Refreshment Breaks/Lunch in Exhibit Hall

Workshops:
Thursday, May 16
2 pm - 5:30 pm

Technical Program:
May 15-16, 2002

Session 1: Wireless Modules
Session Chairs: Jim Laite, Signetics; Marc Papageorge, AIT, Inc.

Session 2: MOEMS
Session Chairs: Steve Anderson, Silicon Bandwidth; J.C. Chiao, Chorum Technologies

Session 3: Subsystem Manufacture
Session Chairs: Gary Tanel, NPRC, Inc.; Frank Henry, Alcatel

Session 4: Design Partitioning
Session Chairs: Charles Bauer, TechLead Corporation; Michael Pecht, University of Maryland

Session 5: Broadband Data Transmission
Session Chairs: J.C. Chiao, Chorum Technologies; Brian Crowe, TELE-WORX

Session 6: Test Strategies and Thermal Management Solutions
Session Chairs: Roger Emigh, STATS; Edward Sayre, North East Systems Associates (NESA)

Session 7: Subsystem Modules
Session Chairs: Brenda Estrada, Alcatel; Nick Leonardi, Auer Precision

PDCs

PDC1:
Integrated Packaging Technologies for Low Cost Functionality; MCMs, 3D & Optoelectronics
9 am - Noon

Instructor:
Charles E. Bauer, Ph.D., TechLead Corporation

Course Description:
Market demands for complex functionality combined with short time to profitability drive increasing importance for system in package (SiP) or integrated packaging technologies. This course provides an in depth understanding of SiP through a combination of case studies and basic building block technology reviews. Topical coverage includes design partitioning and cost benefit analysis as well as materials, process and structure technology trade offs and selection. Identification of technical challenges presented by module test, passive component integration and optical/optoelectronic devices completes this course in SiP technologies and their application. By attending this course you will gain an improved understanding and selection of integrated packaging technologies as well as gain knowledge of state-of-the-art system in package (SiP) technologies worldwide. You will understand the materials, processes and structures of integrated packages and gain insight into performance and cost trade-offs among functional module packaging alternatives.

Who Should Attend?
This course covers basic and advanced topics for product engineers, design engineers, manufacturing process engineers, assembly/packaging engineers, engineering managers, senior design technicians, consultants and academic specialists as well as marketing and sales personnel requiring an understanding of the emerging field of integrated or system in package technologies.

Instructor Biography:
Charles E. Bauer, Ph.D. is senior managing director of TechLead Corporation, a technology management company specializing in the electronics packaging, interconnection and assembly industry. Dr. Bauer focuses in the area of strategic technology planning and selection, particularly the interaction between markets and technology applications. He has more than 20 years of experience spanning the range from printed circuit board and hybrid fabrication through complex IC metallization, multilayer packaging, multichip modules and flat panel display packaging and assembly. Recent target technology areas include ball grid array (BGA), flip chip and chip scale packaging (CSP); 3D, MEMS and optoelectronic assembly; and the cost benefit analysis of design partitioning and technology selection trade offs.

PDC2:
Simplified Assembly for Low Cost
9 am - Noon

Instructor:
Rich Freiberger, Industry Consultant

Course Description:
In today’s challenging and competitive environment, products experience price pressures in many areas of the development process. This course will focus on several areas that can simplify or reduce the overall cost associated with the manufacturing process. Discussions will include areas of design, assembly, automation and test. The discussions will include a review of the manufacturing steps and ways to reduce costs associated with the different activities.

As a participant in this course you will learn ways of comparing cost during the DFM/DFT process, different approaches to the development of an assembly process, and different approaches to the test process.

Who Should Attend?
Process and test engineers, manufacturing professionals, and operations staff interested in cost reductions.

Instructor Biography:
Rich Freiberger has over 28 years in the high tech industry with a specialty in surface mount and companion technology. Most recently Mr. Freiberger served as CTO of ACT Manufacturing. He has considerable manufacturing expertise in areas from high volume/low mix, low volume/high mix, high frequency RF, direct chip attach for high volume RF, and Fine Pitch Area Array Technology. He has served on the Board of the SMTA for 6 years as the Vice President of Technical Programs. He has assisted several companies as an Advisory Board Member with New Product introduction expertise. Rich has published numerous articles on a variety of manufacturing topics. He is currently working in a consulting capacity to develop new product methodologies for a pre-IPO company.

PDC3:
DFX for Wireless Telecommunications
9 am - Noon

Instructor:
Dale Lee, Valor Computerized Systems

Course Description:
Telecommunications consumers today are demanding and receiving product designs that are smaller, more powerful, user friendly, portable and less costly than previous products. These demands have increased the usage of advanced materials, high-density printed circuit boards, component packaging, manufacturing processes, inspection methods and test processes in accordance with product development program objectives. In addition, legislative requirements are imposing new requirements of lead free attachment, recycle and others on product development programs. With the increased usage of subcontracted services (Design, Supply Chain Management, Assembly and Test) by OEM’s for development of their products, the availability of DFM/DFT skills within the OEM needed for the review on new product designs will decrease. This program will provide an exposure to DFM/DFT program concepts, component design/selection, and availability of automated tools to provide DFM/DFT input into the product design.

Who Should Attend?
This course will be of value to circuit board designers, packaging engineers, design, manufacturing, supply chain and program professionals and managers involved with product development where DFM/DFT is an element of the program or simply want general information on what is involved in conduction a successful DFM/DFT program.

Instructor Biography:
Dale Lee is product marketing manager for Valor Computerized Systems. He has been involved in surface mount design, package and process development and production for over 20 years in various technical and managerial positions. These activities have included the research, development and implementation of advanced manufacturing technologies and interconnect techniques; the design and development of CSP and BGA packages, PCB and PCBA support; customer DFX analysis of flex and rigid PCB/PCBAs including supply chain, process qualification and new process introduction for low, medium and high volume production applications.

Technical Program Schedule

Wednesday, May 15

Registration
8 am - 7:30 pm

Professional Development Courses
9 am - NOON

Exhibit Opens
10 am - 7:30 pm

Luncheon in Exhibit Hall
Noon - 1 pm

Keynote Presentation
1 pm - 1:45 pm
Memory Modulization Strategy for Wireless Appliances
Speaker: Kim Il Ung, VP, Samsung Electronics

Session 1: Wireless Modules
2 pm - 5 pm
Session Chairs: Jim Laite, Signetics; Marc Papageorge, AIT, Inc.

Progression Towards a Fully Integrated RF Transceiver Module
Mark Christensen, Prismark Partners LLC

Low Profile Transformers Using Low Temperature Co-Fire Magnetic Tape
John Bielawski and George Slama, Nascentechnology a Division of Midcom, Inc.; A.H. Feingold, C.Y.D. Huang, M.R. Heinz, R.L. Wahlers, ElectroScience Laboratories

Planar Transformers
Charles Tapscott, M-Flex

Break: 3:30 pm - 4 pm

Novel Packaging Approaches for Miniature Antennas
Will McKenzie, Greg Mendolia, Jim McDonald, e-tenna Corporation

History, Trends and Issues Related to Microprocessor Packages used in Handheld Wireless Products
Tom Gregorich, Ed Reyes, Qualcomm

Session 2: MOEMS
2 pm - 5:30 pm
Session Chairs: Steve Anderson, Silicon Bandwidth;
J.C. Chiao, Chorum Technologies

A View of Tomorrow’s Optical Packaging Technology
Harry Bonham, Chorum Technologies

Film Insert Molding for Lenses
Joe Romano, Uniplas Corporation

Optoelectronic Packaging: Meeting, Not Exceeding Application Requirements
Leo M. Higgins III, Ph.D., Siemens Dematic EAS

Break: 3:30 pm - 4 pm

Low Cost Optoelectronic Component Fabrication and Packaging
Donald J. Hayes, Ting Chen, and W. Royall Cox, MicroFab Technologies, Inc.

X-ray Inspection for Optoelectronic Components-The Role of Advanced Detector Technology
Vikram Butani, V.J. ElectroniX

Accelerated Life Testing Considerations in Photonics
Ephraim Suhir, Iolon, Inc.

Session 3: Subsystem Manufacture
2 pm - 5:30 pm
Session Chairs: Gary Tanel, NPRC, Inc.; Frank Henry, Alcatel

Splicing Loss Control and Assembly Yield Management
Bert Zamzow, Corning Cable Systems GmbH and Co.; Katsuji Takasu, Siemens Dematic Electronic Assembly Systems, Inc.

Life Prediction of Lead-Free Solder Joints for Handheld Product Application
Dongji Xie, Minna Arra, Hoang Phan, Dongkai Shangguan, David Geiger, Sammy Yi, Flextronics

Advantages of Direct Part Marking in Electronic Circuit Board Assembly and Test
David S. Thorpe, Thorpe Technical Services, LCC, Consultant to RVSI Acuity Ci Matrix

Break: 3:30 pm - 4 pm

Assessing the Effect of Fine Pitch BGA Packages on Motherboard Design and Board Level Reliability
Michael Leoni, David Paten, Motorola SPS

PCB Design Optimization of 0201 Packages for High Density Electronics Product
Mei Wang, Dongkai Shangguan, David Geiger, Fredrik Mattsson, Sammy Yi, Flextronics

Thermally Conductive Silicone Adhesives and Elastomers for High Thermally Stressed Assembly
Jesus Marin, Dow Corning Corporation

Thursday, May 16

Registration
8 am - 5:30 pm

Exhibit Opens
10 am - 4 pm

Session 4: Design Partitioning
8 am - 11 am
Session Chairs: Charles Bauer, TechLead Corporation;
Michael Pecht, University of Maryland

Physical Layer Solutions for Very Short Reach Applications Utilizing Parallel Optics
Steve Hart, Agilent Technologies

Partitioning Efficiency for Wireless Appliances
Charles Bauer, TechLead Corporation

IBIS Modeling and Simulation of High Speed Fiber-Optic Transceivers
Herbert Lage, Agilent Technologies

Break: 9:30 am - 10 am

Gigabit Ethernet and SAN Protocol Transport
Charlie Roach, Applied Micro Circuits Corporation

The Foundation Blocks for the Next Generation Network Elements
Charlie Roach, Applied Micro Circuits Corporation

Session 5: Broadband Data Transmission
8 am - 11:30 am
Session Chairs: J.C. Chiao, Chorum Technologies;
Brian Crowe, TELE-WORX

Mobile Operator Based WLAN
Ram Velidi, Sevin Rosen

Synthesizer-Based High Frequency, Low Phase Jitter Oscillator Design
Tom Knecht, CTS Wireless

RF MEMS Devices for Wireless Communication
J.B. Lee, University of Texas at Dallas

Break: 9:30 am - 10 am

Dynamic Optical Filtering in DWDM Systems using the DMD
Walter Duncan, Texas Instruments

Telecom Component Multi-Source Agreements and Their Effects on Optoelectronics
Amy Dugan, iPhotonics

Microassembly with Silicon Microfabricated Components
Matthew Ellis, Zyvex

Session 6: Test Strategies and Thermal
Management Solutions
8 am - 11:30 am
Session Chairs: Roger Emigh, STATS;
Edward Sayre, North East Systems Associates (NESA)

Optimizing Test Strategies during PCB Design for Boards with Limited ICT Access
Amit Verma, Charles Robinson, Teradyne, Inc.

New Method for Measuring Attenuation Performance of Electromagnetic Interference Shielding Systems for Small Wireless Devices
Robert Foster, Douglas Nobbs, David Rich, Robert Stiffler, Stanley Tozlowski, Daniel Ventura, Chomerics Division of Parker Hannifin Corporation

System-Level Packaging of Telecommunications Systems: A Design Guide for Optimal Flow Performance
Izuh Obinelo, Degree Controls, Inc.

Break: 9:30 am - 10 am

A Novel Approach to Thermal Management and EMI Shielding Vis a Metallic Conformal Coating on a Plastic Housing
John Hannafin, George Watchko, Chomerics, Division of Parker Hannifin

Thermal Characterization of Small Form Factor Transceivers for a Multi-Port Application
Steve Bowers, Agilent Technologies

Thermal Considerations for 10Gb Ethernet Packaging Solutions
Keith Bailey, Roger Emigh, STATS

Lunch: Noon - 1 pm in Exhibit Hall

Keynote Presentation
1 pm - 2 pm
TBD

Session 7: Subsystem Modules
2 pm - 4:30 pm
Session Chairs: Brenda Estrada, Alcatel;
Nick Leonardi, Auer Precision

Assembly of Telecom Hardware Modules, Based on Innovative Capillary Connection (C2) Technology
A. Taran, A.Belov, V. Krivoshapko, Microelectronics Assembly Innovations

Solutions to Meet Hand-held Market’s Requirement for Low Cost Advanced Reflow and Environmentally Sensitive Packaging
Fonzell Martin, Trent Thompson, Motorola SPS

Finger Print Sensor for Cell Phones
Guy Immega, Niall Parker, Kinetic Sciences, Inc.

Break: 3:30 pm - 4 pm

Design, Manufacturability, and Reliability Considerations for Baseband and Memory Stacked Die System in Package Solutions
Mark Gerber, Jeannie Miller, Trent Thompson, Motorola SPS

Workshops

Workshop 1:
Addressing the Challenges of BluetoothTM
System Design
2 pm - 3:30 pm

Speaker: Bill Byrom, Tektonix

Workshop Description:
This presentation will cover the challenges of Bluetooth System Design: From Initial Chipset Design to Final Qualification and Conformance Testing. It will also include the latest Bluetooth test solutions from Tektronix.

Who Should Attend?
Engineers and managers responsible for designing or manufacturing Bluetooth components and systems. If you are concerned about Bluetooth Physical, transport, and protocol layer testing, this is an excellent workshop for you.

Workshop 2:
High Volume Optical Assembly
2 pm - 3:30 pm

Speaker: Stanford Crane & Steve Anderson, Silicon Bandwidth

Workshop Description:
This workshop will discuss the challenges and issues facing component and system manufacturers who want to develop more cost effective component and sub-system solutions for optical packaging as well as opto-electronic integration. Issues such as increasing bandwidth throughout the system and newer technologies for optical components will be addressed.

Sections:
I. Overview of optical assembly challenges and high-volume requirements.
II. Introductions in next generation high speed optical components.
III. Bandwidth and performance bottlenecks affecting high-volume assembly.
IV. Direction in improving thermal and electrical performance.
V. Optic packaging considerations and new material developments.
VI. Automation of optical packages using design for manufacturability and improved process considerations.

Who Should Attend?
No previous Optics packaging experience is required as this workshop will cover the basics followed by an introduction into new methods and procedures. The workshop will benefit technologists and businesspeople who want to gain an understanding of developments in the optical packaging particularly those aimed at reducing the cost of substrates and modules and improving both the automation level of these devices as well as the performance.

Workshop 3:
Using Reliability Predictions for Telecom System Designs
2 pm - 3:30 pm

Speaker: Michael Pecht, University of Maryland

Workshop Description:
There are many reliability prediction methods that can be used in the design of telecom systems. When using a method, the IEEE Reliability Prediction Standard 1413 requires that sufficient information concerning inputs, assumptions, and uncertainties are included, so that the risks associated with using the prediction are understood. The goal of IEEE 1413 was to bring transparency to the reliability predictions and to positively affect the telecommunications industry, which has used, and in some cases continues to use, outdated U.S. military-based predictions methodologies, such as the Telcordia SR-332 prediction method. This workshop presents the IEEE 1413 Standard, and discusses how it should be used, its influence on those that use Telcordia SR-332 reliability prediction methods, and its overall impact on the telecommunications industry. There will also be a discussion of other reliability prediction methods and their value in telecom equipment design.

Who Should Attend?
The course is for those in the telecommunications industry, who are engaged in product design, quality and reliability assessments, standards, and contract negotiations. It is also for those who need to assess the value provided by the Telcordia specifications and standards.
Break: 3:30 pm - 4 pm

Workshop 4:
MEMS in Telecom
4 pm - 5:30 pm

Speaker: Ken Gilleo, Cookson Electronics

Workshop Description:
The workshop will overview MEMS (Micro-Electro-Mechanical Systems) including fabrication methods, designs, functionality and applications. A brief description of Internet architecture and hardware will be included for background. The main theme will be on non-optical MEMS devices that can serve the telecom industry, especially RF-MEMS. We will discus principles, categories, applications and benefits for RF-MEMS. Topics include MEMS switches, relays, inductors, capacitors, filters, resonators and dynamic antennas. Specific devices will be examined. Finally, we’ll attempt to predict the future of MEMS in telecom.

Who Should Attend?
No previous MEMS knowledge is needed since basics will be covered. The workshop will benefit technologists and businesspersons in both portable and land-based communications especially those involved in wireless. It will also be of interest to IC fabricators and advanced packagers.

Workshop 5:
MCM Reliability
4 pm - 5:30 pm

Speaker: Horatio Quinones, ASYMTEK

Workshop Description:
This workshop will include a variety of topics including flip chip and CSP technology: Specific topics covered:
- A Historic Perspective
- Flip Chip on: ceramics, organic, carriers
- Flip Chip on board, DCA
- Flip Chip encapsulation:
- Reliability improvement
- Failure Mechanisms
- Accelerated Thermal Cycle data
- Underfill processes for FC
Encapsulation methods (capillary underfill and compression flow underfill, “no-flow underfill”) and reliability statistics (data analysis, MCM reliability assessment in the presence of temperature excursions, green cycles ,reliability projections for MCM’s in the presence of random environments, and statistics of crack initiation and propagation, and SCRIP statistics) will all be discussed. At the end of this lecture the student will have an understanding of how to assess reliability performance of MCM’s compared to SCM’s. The student will be able to use close form equations to readily evaluate wearout mechanisms of MCM interconnections design TV to maximize data gathering.

Who Should Attend?
This course will be beneficial to design and reliability engineers, quality managers, and packaging engineers in general.