UTA Department of Mathematics

Applied Mathematics Seminar

Date/Time/Room: Thursday (10/26/2006) at 2:00pm in 304 Pickard Hall

Speaker: Dr. Kevin Wadleigh
High Performance Computing Division
Hewlett-Packard Company

"High Performance Computing: Math, Computers, and Accelerators"

Abstract: For many years microprocessor performance has increased at rates consistent with Moore's Law for transistors. In the 1970s-1990s the improvement was mostly obtained by increasing clock frequencies. Now that clock speeds are improving slowly, microprocessor vendors are increasing the number of cores per chip to obtain improved performance. This approach is not allowing single threads of execution to increase performance at the rates users have come to expect. Therefore many are investigating alternative technologies such as General Purpose Graphical Processing Units (GPGPUs), Field Programmable Gate Arrays (FPGAs), ClearSpeed's floating-point boards and IBM's Cell systems. Unfortunately performance expectations are frequently unrealistic due to very high theoretical peak rates, but very low sustainable ones. In addition the software development environment for many of the technologies is cumbersome for most software developers.

The high performance computing (HPC) discipline consists of applications that have extreme computational requirements. It's dominated by applications that use 64-bit floating-point calculations and these frequently have little data reuse. HPC applications are built on top of well known basic mathematical algorithms. These algorithms have been analyzed to determine how well they map to accelerators and therefore which accelerators hold the most promise for HPC customers.