Semiconductor devices - The needs and the technological challenges
Ruigang Li, Ph.D
Senior Scientist, IEEE Senior Member, ICDS
4:00 PM, 10/4/06, UTA Physics
CMOS is the mainstream of current semiconductor industry. As the scale of integration and complexity continues to increase, the physical limitation and process challenge for conventional MOSFET has become a primary bottleneck. Present research works have shown that the strained channel, high-K and metal gate, Fin-FET structure and low-K dielectric material for interconnection can help increase mobility and suppress the gate tunneling, short channel effect and propagation delay so that the higher speed and integration density can be achieved. 193-nm immersion lithography can be extended to 22-nm node by extremely high transmission fluid of index. The EUV (13.4nm wavelength) technology is still under evaluation because of source power and photo resist sensitivity.
This talk focuses on power dissipation, speed, integration density, functionality and cost of CMOS. Various CMOS, such as conventional bulk CMOS, SOI CMOS, SiGe Strained Si CMOS and vertical surrounding gate CMOS are discussed.