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Rethinking Harmonic-Rejection Mixer and Digital Phase-Locked-Loop -- A Systems Perspective

Friday, March 31, 2017, 11:00 AM - 12:00 PM
Nedderman Hall Room 112

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Won Namgoong, Ph.D.,

Professor of Electrical Engineering, UTD


In this talk, we revisit two widely employed circuit blocks, namely harmonic-rejection mixer (HRM) and digital phase-locked-loop (DPLL). HRMs are used in wideband receivers to reduce the mixing of spurious harmonic tones, whose overall performance is limited by gain and phase mismatches. By viewing the harmonic distortion problem as a multiuser detection problem in communications, digital compensation techniques can be devised to significantly improve HRM performance. Furthermore, the insights gained from this perspective can be used to develop new HRM architectures with numerous implementation advantages. A prototype chip has been built as proof of concept.

In DPLL, the use of time-to-digital converter and digitally-controlled oscillator enable the loop filter to be fully digital. Instead of digitizing the loop filter of an analog PLL as has been conventionally done, more sophisticated control schemes can be employed to achieve improved performance. An observer-controller DPLL is proposed, whose loop filter is designed in the time domain, instead of using poles and zeros in the frequency domain as conventionally done. The primary advantage is that it provides additional degrees of freedom that can be used to account for loop latency and supply noise.


Won Namgoong is a professor of electrical engineering at The University of Texas at Dallas. He earned a B.S. degree in electrical engineering and computer science from the University of California at Berkeley, and M.S. and Ph.D degrees in electrical engineering from Stanford University. His research activities are in signal processing systems and RF/analog circuits. He is particularly interested in DSP-assisted analog circuits and systems.

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