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EE Seminar: Energy-Efficient Beyond-CMOS Nanoelectronic Device, Circuit, and System

Monday, September 30, 2019, 11:00 AM - 12:00 PM
Nedderman Hall Rm 203

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Chenyun Pan, Ph.D.
Assistant Professor, UTA Department of Electrical Engineering


Decades of continuous CMOS technology scaling has brought us significant improvement in computing capability and the cost reduction of microprocessors. However, this scaling is approaching its physical limits. Many beyond-CMOS technologies have been proposed to augment or even replace the conventional CMOS technology and to sustain the exponential growth of computational power. Despite large research effort, no single beyond-CMOS device or material has been identified as a simple drop-in replacement for CMOS. Most emerging devices have fundamentally different operation principles, and must be complemented with novel circuits, interconnects, memory, and system architectures to achieve their full potential. This requires close interactions and explorations between device technologies and circuits/systems. Therefore, a holistic approach is critical to co-optimize different levels of abstraction for optimal performance of the computing system.

In this talk, I will start with the scaling challenges of CMOS devices and Cu/Low-k interconnects, and introduce several representative beyond-CMOS devices. To fully utilize the unique physics of emerging devices, I will show a bio-inspired neuromorphic circuit, the cellular neural network (CNN), as the computing platform to achieve orders of magnitude improvement in computing efficiency. Next, I will present an efficient hierarchical design methodology that allows optimization across various emerging device-, interconnect-, and system-level innovations for a generic VLSI system. The importance of technology/system co-design will be addressed by several case studies, including deeply scaled nanowire devices, advanced interconnects, and heterogeneous integration for a multi-core processor. I will conclude the talk with future directions to enable energy-efficient computing.


Chenyun PanChenyun Pan is an assistant professor in the Department of Electrical Engineering at UTA. He earned a Ph.D. in the School of Electrical and Computer Engineering at Georgia Tech in 2015. In the summer of 2014 and spring of 2015, he was a researcher at IMEC in Leuven, Belgium, focusing on emerging graphene interconnects and deeply scaled vertical FETs. From 2015-2018, he was a research scientist in the School of ECE at the Georgia Institute of Technology. Before joining UTA, he was an assistant professor at the University of Kansas.

Pan’s research interests cover the modeling and optimization of energy-efficient Boolean and non-Boolean computing systems using various emerging beyond-CMOS devices, interconnects, and memory technologies. He has published more than 40 peer-reviewed IEEE journal and conference papers. He is the recipient of two Best Paper awards in the IEEE International Symposium on Quality Electronic Design and IEEE Conference on IC Design and Technology, and 2018 Research Spotlight Award in the School of ECE at Georgia Tech. More information can be found on his website at

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