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Altera Quartus II 4

Last Review: October 16, 2008

Available To:

  • Students Admitted to UT Arlington
  • Faculty (currently appointed) and Staff

Version: 4.1

Standard Software Supported By: Labs

OIT Support Levels: Minimal


Quartus II is Altera's VHDL and Verilog development software.

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest area, lowest power consumption, highest clock speed, or other requirements.

Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (later renamed to Gateway Design Automation) in 1985 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.

System Requirements: Mfg. minimum

  • Base OS: Windows
  • OS Version: XP

System Requirements: OIT Required

  • Base OS: Windows
  • OS Version: XP SP3

Known Issues:

How to Get:

Quartus II is not free software, but a trial version is downloadable from



Altera's Quartus II Support Center

Related Software:

VASG - VHDL Analysis and Standardization Group

IEEE Verilog standard